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i2c-algo-8xx.c @ 3765

Revision 3765, 15.1 KB (checked in by kmalkki, 10 years ago)

(Kyösti) More cleanups

Redo i2c-core locks.

No longer pass controlling_mod in i2cproc_register_entry, use
client->driver->owner instead.

Comment out or remove obsolete parts of mkpatch for 2.5.
Currently it does not touch kernel build/configure system at all.

Cleanup #include order. Note that kernel headers are not to be
included for userland utilities, to promote binary compatibility of
utilities across kernel versions.

Remove bus_scans. Remove empty and unused algo_control and
debugging code that would not compile if uncommented.

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

Line
1	/*
2	* i2c-algo-8xx.c i2x driver algorithms for MPC8XX CPM
3	* Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
4	*
5	This program is free software; you can redistribute it and/or modify
6	it under the terms of the GNU General Public License as published by
7	the Free Software Foundation; either version 2 of the License, or
8	(at your option) any later version.
9
10	This program is distributed in the hope that it will be useful,
11	but WITHOUT ANY WARRANTY; without even the implied warranty of
12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	GNU General Public License for more details.
14
15	You should have received a copy of the GNU General Public License
16	along with this program; if not, write to the Free Software
17	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18	*
19	* moved into proper i2c interface; separated out platform specific
20	* parts into i2c-rpx.c
21	* Brad Parker (brad@heeltoe.com)
22	*/
23
24	// XXX todo
25	// timeout sleep?
26
27	/* $Id$ */
28
29	#include <linux/kernel.h>
30	#include <linux/module.h>
31	#include <linux/delay.h>
32	#include <linux/slab.h>
33	#include <linux/init.h>
34	#include <linux/errno.h>
35	#include <linux/sched.h>
36	#include "i2c.h"
37	#include "i2c-algo-8xx.h"
38	#include <asm/mpc8xx.h>
39	#include <asm/commproc.h>
40
41
42	#define CPM_MAX_READ 513
43	/* #define I2C_CHIP_ERRATA / / Try uncomment this if you have an older CPU(earlier than rev D4) */
44	static wait_queue_head_t iic_wait;
45	static ushort r_tbase, r_rbase;
46
47	int cpm_debug = 0;
48
49	static void
50	cpm_iic_interrupt(void dev_id, struct pt_regs regs)
51	{
52	volatile i2c8xx_t i2c = (i2c8xx_t )dev_id;
53	if (cpm_debug > 1)
54	printk("cpm_iic_interrupt(dev_id=%p)\n", dev_id);
55	#if 0
56	/* Chip errata, clear enable. This is not needed on rev D4 CPUs */
57	/* This should probably be removed and replaced by I2C_CHIP_ERRATA stuff */
58	/* Someone with a buggy CPU needs to confirm that */
59	i2c->i2c_i2mod &= ~1;
60	#endif
61	/* Clear interrupt.
62	*/
63	i2c->i2c_i2cer = 0xff;
64
65	/* Get 'me going again.
66	*/
67	wake_up_interruptible(&iic_wait);
68	}
69
70	static void
71	cpm_iic_init(struct i2c_algo_8xx_data *cpm)
72	{
73	volatile iic_t *iip = cpm->iip;
74	volatile i2c8xx_t *i2c = cpm->i2c;
75	unsigned char brg;
76	bd_t bd = (bd_t )__res;
77
78	if (cpm_debug) printk(KERN_DEBUG "cpm_iic_init()\n");
79
80	/* Initialize the parameter ram.
81	* We need to make sure many things are initialized to zero,
82	* especially in the case of a microcode patch.
83	*/
84	iip->iic_rstate = 0;
85	iip->iic_rdp = 0;
86	iip->iic_rbptr = 0;
87	iip->iic_rbc = 0;
88	iip->iic_rxtmp = 0;
89	iip->iic_tstate = 0;
90	iip->iic_tdp = 0;
91	iip->iic_tbptr = 0;
92	iip->iic_tbc = 0;
93	iip->iic_txtmp = 0;
94
95	/* Set up the IIC parameters in the parameter ram.
96	*/
97	iip->iic_tbase = r_tbase = cpm->dp_addr;
98	iip->iic_rbase = r_rbase = cpm->dp_addr + sizeof(cbd_t)*2;
99
100	iip->iic_tfcr = SMC_EB;
101	iip->iic_rfcr = SMC_EB;
102
103	/* Set maximum receive size.
104	*/
105	iip->iic_mrblr = CPM_MAX_READ;
106
107	/* Initialize Tx/Rx parameters.
108	*/
109	if (cpm->reloc == 0) {
110	volatile cpm8xx_t *cp = cpm->cp;
111
112	cp->cp_cpcr =
113	mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) \| CPM_CR_FLG;
114	while (cp->cp_cpcr & CPM_CR_FLG);
115	} else {
116	iip->iic_rbptr = iip->iic_rbase;
117	iip->iic_tbptr = iip->iic_tbase;
118	iip->iic_rstate = 0;
119	iip->iic_tstate = 0;
120	}
121
122	/* Select an arbitrary address. Just make sure it is unique.
123	*/
124	i2c->i2c_i2add = 0xfe;
125
126	/* Make clock run at 60 KHz.
127	*/
128	brg = (unsigned char) (bd->bi_intfreq/(32260000) -3);
129	i2c->i2c_i2brg = brg;
130
131	i2c->i2c_i2mod = 0x00;
132	i2c->i2c_i2com = 0x01; /* Master mode */
133
134	/* Disable interrupts.
135	*/
136	i2c->i2c_i2cmr = 0;
137	i2c->i2c_i2cer = 0xff;
138
139	init_waitqueue_head(&iic_wait);
140
141	/* Install interrupt handler.
142	*/
143	if (cpm_debug) {
144	printk ("%s[%d] Install ISR for IRQ %d\n",
145	__func__,__LINE__, CPMVEC_I2C);
146	}
147	(cpm->setisr)(CPMVEC_I2C, cpm_iic_interrupt, (void )i2c);
148	}
149
150
151	static int
152	cpm_iic_shutdown(struct i2c_algo_8xx_data *cpm)
153	{
154	volatile i2c8xx_t *i2c = cpm->i2c;
155
156	/* Shut down IIC.
157	*/
158	i2c->i2c_i2mod &= ~1;
159	i2c->i2c_i2cmr = 0;
160	i2c->i2c_i2cer = 0xff;
161
162	return(0);
163	}
164
165	static void
166	cpm_reset_iic_params(volatile iic_t *iip)
167	{
168	iip->iic_tbase = r_tbase;
169	iip->iic_rbase = r_rbase;
170
171	iip->iic_tfcr = SMC_EB;
172	iip->iic_rfcr = SMC_EB;
173
174	iip->iic_mrblr = CPM_MAX_READ;
175
176	iip->iic_rstate = 0;
177	iip->iic_rdp = 0;
178	iip->iic_rbptr = iip->iic_rbase;
179	iip->iic_rbc = 0;
180	iip->iic_rxtmp = 0;
181	iip->iic_tstate = 0;
182	iip->iic_tdp = 0;
183	iip->iic_tbptr = iip->iic_tbase;
184	iip->iic_tbc = 0;
185	iip->iic_txtmp = 0;
186	}
187
188	#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
189	#define BD_SC_OV ((ushort)0x0002) /* OV - receive overrun */
190	#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
191
192	static void force_close(struct i2c_algo_8xx_data *cpm)
193	{
194	volatile i2c8xx_t *i2c = cpm->i2c;
195	if (cpm->reloc == 0) { /* micro code disabled */
196	volatile cpm8xx_t *cp = cpm->cp;
197
198	if (cpm_debug) printk("force_close()\n");
199	cp->cp_cpcr =
200	mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_CLOSE_RXBD) \|
201	CPM_CR_FLG;
202
203	while (cp->cp_cpcr & CPM_CR_FLG);
204	}
205	i2c->i2c_i2cmr = 0x00; /* Disable all interrupts */
206	i2c->i2c_i2cer = 0xff;
207	}
208
209
210	/* Read from IIC...
211	* abyte = address byte, with r/w flag already set
212	*/
213	static int
214	cpm_iic_read(struct i2c_algo_8xx_data cpm, u_char abyte, char buf, int count)
215	{
216	volatile iic_t *iip = cpm->iip;
217	volatile i2c8xx_t *i2c = cpm->i2c;
218	volatile cpm8xx_t *cp = cpm->cp;
219	volatile cbd_t tbdf, rbdf;
220	u_char *tb;
221	unsigned long flags, tmo;
222
223	if (count >= CPM_MAX_READ)
224	return -EINVAL;
225
226	/* check for and use a microcode relocation patch */
227	if (cpm->reloc) {
228	cpm_reset_iic_params(iip);
229	}
230
231	tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
232	rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase];
233
234	/* To read, we need an empty buffer of the proper length.
235	* All that is used is the first byte for address, the remainder
236	* is just used for timing (and doesn't really have to exist).
237	*/
238	tb = cpm->temp;
239	tb = (u_char *)(((uint)tb + 15) & ~15);
240	tb[0] = abyte; /* Device address byte w/rw flag */
241
242	flush_dcache_range((unsigned long) tb, (unsigned long) (tb+1));
243
244	if (cpm_debug) printk("cpm_iic_read(abyte=0x%x)\n", abyte);
245
246	tbdf->cbd_bufaddr = __pa(tb);
247	tbdf->cbd_datlen = count + 1;
248	tbdf->cbd_sc =
249	BD_SC_READY \| BD_SC_LAST \|
250	BD_SC_WRAP \| BD_IIC_START;
251
252	iip->iic_mrblr = count +1; /* prevent excessive read, +1
253	is needed otherwise will the
254	RXB interrupt come too early */
255
256	/* flush will invalidate too. */
257	flush_dcache_range((unsigned long) buf, (unsigned long) (buf+count));
258
259	rbdf->cbd_datlen = 0;
260	rbdf->cbd_bufaddr = __pa(buf);
261	rbdf->cbd_sc = BD_SC_EMPTY \| BD_SC_WRAP\| BD_SC_INTRPT;
262	if(count > 16){
263	/* Chip bug, set enable here */
264	local_irq_save(flags);
265	i2c->i2c_i2cmr = 0x13; /* Enable some interupts */
266	i2c->i2c_i2cer = 0xff;
267	i2c->i2c_i2mod \|= 1; /* Enable */
268	i2c->i2c_i2com \|= 0x80; /* Begin transmission */
269
270	/* Wait for IIC transfer */
271	tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
272	local_irq_restore(flags);
273	} else { /* busy wait for small transfers, its faster */
274	i2c->i2c_i2cmr = 0x00; /* Disable I2C interupts */
275	i2c->i2c_i2cer = 0xff;
276	i2c->i2c_i2mod \|= 1; /* Enable */
277	i2c->i2c_i2com \|= 0x80; /* Begin transmission */
278	tmo = jiffies + 1*HZ;
279	while(!(i2c->i2c_i2cer & 0x11 \|\| time_after(jiffies, tmo))); /* Busy wait, with a timeout */
280	}
281
282	if (signal_pending(current) \|\| !tmo){
283	force_close(cpm);
284	if(cpm_debug)
285	printk("IIC read: timeout!\n");
286	return -EIO;
287	}
288	#ifdef I2C_CHIP_ERRATA
289	/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
290	Disabling I2C too early may cause too short stop condition */
291	udelay(4);
292	i2c->i2c_i2mod &= ~1;
293	#endif
294	if (cpm_debug) {
295	printk("tx sc %04x, rx sc %04x\n",
296	tbdf->cbd_sc, rbdf->cbd_sc);
297	}
298
299	if (tbdf->cbd_sc & BD_SC_READY) {
300	printk("IIC read; complete but tbuf ready\n");
301	force_close(cpm);
302	printk("tx sc %04x, rx sc %04x\n",
303	tbdf->cbd_sc, rbdf->cbd_sc);
304	}
305
306	if (tbdf->cbd_sc & BD_SC_NAK) {
307	if (cpm_debug)
308	printk("IIC read; no ack\n");
309	return -EREMOTEIO;
310	}
311
312	if (rbdf->cbd_sc & BD_SC_EMPTY) {
313	/* force_close(cpm); */
314	if (cpm_debug){
315	printk("IIC read; complete but rbuf empty\n");
316	printk("tx sc %04x, rx sc %04x\n",
317	tbdf->cbd_sc, rbdf->cbd_sc);
318	}
319	return -EREMOTEIO;
320	}
321
322	if (rbdf->cbd_sc & BD_SC_OV) {
323	if (cpm_debug)
324	printk("IIC read; Overrun\n");
325	return -EREMOTEIO;;
326	}
327
328	if (cpm_debug) printk("read %d bytes\n", rbdf->cbd_datlen);
329
330	if (rbdf->cbd_datlen < count) {
331	if (cpm_debug)
332	printk("IIC read; short, wanted %d got %d\n",
333	count, rbdf->cbd_datlen);
334	return 0;
335	}
336
337	return count;
338	}
339
340	/* Write to IIC...
341	* addr = address byte, with r/w flag already set
342	*/
343	static int
344	cpm_iic_write(struct i2c_algo_8xx_data cpm, u_char abyte, char buf,int count)
345	{
346	volatile iic_t *iip = cpm->iip;
347	volatile i2c8xx_t *i2c = cpm->i2c;
348	volatile cpm8xx_t *cp = cpm->cp;
349	volatile cbd_t *tbdf;
350	u_char *tb;
351	unsigned long flags, tmo;
352
353	/* check for and use a microcode relocation patch */
354	if (cpm->reloc) {
355	cpm_reset_iic_params(iip);
356	}
357	tb = cpm->temp;
358	tb = (u_char *)(((uint)tb + 15) & ~15);
359	tb = abyte; / Device address byte w/rw flag */
360
361	flush_dcache_range((unsigned long) tb, (unsigned long) (tb+1));
362	flush_dcache_range((unsigned long) buf, (unsigned long) (buf+count));
363
364	if (cpm_debug) printk("cpm_iic_write(abyte=0x%x)\n", abyte);
365
366	/* set up 2 descriptors */
367	tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
368
369	tbdf[0].cbd_bufaddr = __pa(tb);
370	tbdf[0].cbd_datlen = 1;
371	tbdf[0].cbd_sc = BD_SC_READY \| BD_IIC_START;
372
373	tbdf[1].cbd_bufaddr = __pa(buf);
374	tbdf[1].cbd_datlen = count;
375	tbdf[1].cbd_sc = BD_SC_READY \| BD_SC_INTRPT \| BD_SC_LAST \| BD_SC_WRAP;
376
377	if(count > 16){
378	/* Chip bug, set enable here */
379	local_irq_save(flags);
380	i2c->i2c_i2cmr = 0x13; /* Enable some interupts */
381	i2c->i2c_i2cer = 0xff;
382	i2c->i2c_i2mod \|= 1; /* Enable */
383	i2c->i2c_i2com \|= 0x80; /* Begin transmission */
384
385	/* Wait for IIC transfer */
386	tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
387	local_irq_restore(flags);
388	} else { /* busy wait for small transfers, its faster */
389	i2c->i2c_i2cmr = 0x00; /* Disable I2C interupts */
390	i2c->i2c_i2cer = 0xff;
391	i2c->i2c_i2mod \|= 1; /* Enable */
392	i2c->i2c_i2com \|= 0x80; /* Begin transmission */
393	tmo = jiffies + 1*HZ;
394	while(!(i2c->i2c_i2cer & 0x12 \|\| time_after(jiffies, tmo))); /* Busy wait, with a timeout */
395	}
396
397	if (signal_pending(current) \|\| !tmo){
398	force_close(cpm);
399	if(cpm_debug && !tmo)
400	printk("IIC write: timeout!\n");
401	return -EIO;
402	}
403
404	#if I2C_CHIP_ERRATA
405	/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
406	Disabling I2C too early may cause too short stop condition */
407	udelay(4);
408	i2c->i2c_i2mod &= ~1;
409	#endif
410	if (cpm_debug) {
411	printk("tx0 sc %04x, tx1 sc %04x\n",
412	tbdf[0].cbd_sc, tbdf[1].cbd_sc);
413	}
414
415	if (tbdf->cbd_sc & BD_SC_NAK) {
416	if (cpm_debug)
417	printk("IIC write; no ack\n");
418	return 0;
419	}
420
421	if (tbdf->cbd_sc & BD_SC_READY) {
422	if (cpm_debug)
423	printk("IIC write; complete but tbuf ready\n");
424	return 0;
425	}
426
427	return count;
428	}
429
430	/* See if an IIC address exists..
431	* addr = 7 bit address, unshifted
432	*/
433	static int
434	cpm_iic_tryaddress(struct i2c_algo_8xx_data *cpm, int addr)
435	{
436	volatile iic_t *iip = cpm->iip;
437	volatile i2c8xx_t *i2c = cpm->i2c;
438	volatile cpm8xx_t *cp = cpm->cp;
439	volatile cbd_t tbdf, rbdf;
440	u_char *tb;
441	unsigned long flags, len, tmo;
442
443	if (cpm_debug > 1)
444	printk("cpm_iic_tryaddress(cpm=%p,addr=%d)\n", cpm, addr);
445
446	/* check for and use a microcode relocation patch */
447	if (cpm->reloc) {
448	cpm_reset_iic_params(iip);
449	}
450
451	if (cpm_debug && addr == 0) {
452	printk("iip %p, dp_addr 0x%x\n", cpm->iip, cpm->dp_addr);
453	printk("iic_tbase %d, r_tbase %d\n", iip->iic_tbase, r_tbase);
454	}
455
456	tbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_tbase];
457	rbdf = (cbd_t *)&cp->cp_dpmem[iip->iic_rbase];
458
459	tb = cpm->temp;
460	tb = (u_char *)(((uint)tb + 15) & ~15);
461
462	/* do a simple read */
463	tb[0] = (addr << 1) \| 1; /* device address (+ read) */
464	len = 2;
465
466	flush_dcache_range((unsigned long) tb, (unsigned long) (tb+2));
467
468	tbdf->cbd_bufaddr = __pa(tb);
469	tbdf->cbd_datlen = len;
470	tbdf->cbd_sc =
471	BD_SC_READY \| BD_SC_LAST \|
472	BD_SC_WRAP \| BD_IIC_START;
473
474	rbdf->cbd_datlen = 0;
475	rbdf->cbd_bufaddr = __pa(tb+2);
476	rbdf->cbd_sc = BD_SC_EMPTY \| BD_SC_WRAP \| BD_SC_INTRPT;
477
478	local_irq_save(flags);
479	i2c->i2c_i2cmr = 0x13; /* Enable some interupts */
480	i2c->i2c_i2cer = 0xff;
481	i2c->i2c_i2mod \|= 1; /* Enable */
482	i2c->i2c_i2com \|= 0x80; /* Begin transmission */
483
484	if (cpm_debug > 1) printk("about to sleep\n");
485
486	/* wait for IIC transfer */
487	tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
488	local_irq_restore(flags);
489
490	#ifdef I2C_CHIP_ERRATA
491	/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
492	Disabling I2C too early may cause too short stop condition */
493	udelay(4);
494	i2c->i2c_i2mod &= ~1;
495	#endif
496
497	if (signal_pending(current) \|\| !tmo){
498	force_close(cpm);
499	if(cpm_debug && !tmo)
500	printk("IIC tryaddress: timeout!\n");
501	return -EIO;
502	}
503
504	if (cpm_debug > 1) printk("back from sleep\n");
505
506	if (tbdf->cbd_sc & BD_SC_NAK) {
507	if (cpm_debug > 1) printk("IIC try; no ack\n");
508	return 0;
509	}
510
511	if (tbdf->cbd_sc & BD_SC_READY) {
512	printk("IIC try; complete but tbuf ready\n");
513	}
514
515	return 1;
516	}
517
518	static int cpm_xfer(struct i2c_adapter *adap,
519	struct i2c_msg msgs[],
520	int num)
521	{
522	struct i2c_algo_8xx_data *cpm = adap->algo_data;
523	struct i2c_msg *pmsg;
524	int i, ret;
525	u_char addr;
526
527	for (i = 0; i < num; i++) {
528	pmsg = &msgs[i];
529
530	if (cpm_debug)
531	printk("i2c-algo-8xx.o: "
532	"#%d addr=0x%x flags=0x%x len=%d\n buf=%lx\n",
533	i, pmsg->addr, pmsg->flags, pmsg->len, (unsigned long)pmsg->buf);
534
535	addr = pmsg->addr << 1;
536	if (pmsg->flags & I2C_M_RD )
537	addr \|= 1;
538	if (pmsg->flags & I2C_M_REV_DIR_ADDR )
539	addr ^= 1;
540
541	if (!(pmsg->flags & I2C_M_NOSTART)) {
542	}
543	if (pmsg->flags & I2C_M_RD ) {
544	/* read bytes into buffer*/
545	ret = cpm_iic_read(cpm, addr, pmsg->buf, pmsg->len);
546	if (cpm_debug)
547	printk("i2c-algo-8xx.o: read %d bytes\n", ret);
548	if (ret < pmsg->len ) {
549	return (ret<0)? ret : -EREMOTEIO;
550	}
551	} else {
552	/* write bytes from buffer */
553	ret = cpm_iic_write(cpm, addr, pmsg->buf, pmsg->len);
554	if (cpm_debug)
555	printk("i2c-algo-8xx.o: wrote %d\n", ret);
556	if (ret < pmsg->len ) {
557	return (ret<0) ? ret : -EREMOTEIO;
558	}
559	}
560	}
561	return (num);
562	}
563
564	static u32 cpm_func(struct i2c_adapter *adap)
565	{
566	return I2C_FUNC_SMBUS_EMUL \| I2C_FUNC_10BIT_ADDR \|
567	I2C_FUNC_PROTOCOL_MANGLING;
568	}
569
570	/* -----exported algorithm data: ------------------------------------- */
571
572	static struct i2c_algorithm cpm_algo = {
573	.owner = THIS_MODULE,
574	.name = "MPC8xx CPM algorithm",
575	.id = I2C_ALGO_MPC8XX,
576	.master_xfer = cpm_xfer,
577	.functionality = cpm_func,
578	};
579
580	/*
581	* registering functions to load algorithms at runtime
582	*/
583	int i2c_8xx_add_bus(struct i2c_adapter *adap)
584	{
585	int i;
586	struct i2c_algo_8xx_data *cpm = adap->algo_data;
587
588	if (cpm_debug)
589	printk("i2c-algo-8xx.o: hw routines for %s registered.\n",
590	adap->name);
591
592	/* register new adapter to i2c module... */
593
594	adap->id \|= cpm_algo.id;
595	adap->algo = &cpm_algo;
596
597	i2c_add_adapter(adap);
598	cpm_iic_init(cpm);
599	}
600
601
602	int i2c_8xx_del_bus(struct i2c_adapter *adap)
603	{
604	struct i2c_algo_8xx_data *cpm = adap->algo_data;
605
606	cpm_iic_shutdown(cpm);
607
608	return i2c_del_adapter(adap);
609	}
610
611	EXPORT_SYMBOL(i2c_8xx_add_bus);
612	EXPORT_SYMBOL(i2c_8xx_del_bus);
613
614	MODULE_AUTHOR("Brad Parker <brad@heeltoe.com>");
615	MODULE_DESCRIPTION("I2C-Bus MPC8XX algorithm");
616	MODULE_LICENSE("GPL");

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