root/i2c/trunk/kernel/i2c-algo-ibm_ocp.c @ 3765

Revision 3765, 26.6 KB (checked in by kmalkki, 12 years ago)

(Kyösti) More cleanups

Redo i2c-core locks.

No longer pass controlling_mod in i2cproc_register_entry, use
client->driver->owner instead.

Comment out or remove obsolete parts of mkpatch for 2.5.
Currently it does not touch kernel build/configure system at all.

Cleanup #include order. Note that kernel headers are not to be
included for userland utilities, to promote binary compatibility of
utilities across kernel versions.

Remove bus_scans. Remove empty and unused algo_control and
debugging code that would not compile if uncommented.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
Line 
1/*
2   -------------------------------------------------------------------------
3   i2c-algo-ibm_ocp.c i2c driver algorithms for IBM PPC 405 adapters       
4   -------------------------------------------------------------------------
5     
6   Ian DaSilva, MontaVista Software, Inc.
7   idasilva@mvista.com or source@mvista.com
8
9   Copyright 2000 MontaVista Software Inc.
10
11   Changes made to support the IIC peripheral on the IBM PPC 405
12
13
14   ---------------------------------------------------------------------------
15   This file was highly leveraged from i2c-algo-pcf.c, which was created
16   by Simon G. Vogl and Hans Berglund:
17
18
19     Copyright (C) 1995-1997 Simon G. Vogl
20                   1998-2000 Hans Berglund
21
22   With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
23   Frodo Looijaard <frodol@dds.nl> ,and also from Martin Bailey
24   <mbailey@littlefeet-inc.com>
25
26
27    This program is free software; you can redistribute it and/or modify
28    it under the terms of the GNU General Public License as published by
29    the Free Software Foundation; either version 2 of the License, or
30    (at your option) any later version.
31
32    This program is distributed in the hope that it will be useful,
33    but WITHOUT ANY WARRANTY; without even the implied warranty of
34    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
35    GNU General Public License for more details.
36
37    You should have received a copy of the GNU General Public License
38    along with this program; if not, write to the Free Software
39    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
40   ---------------------------------------------------------------------------
41
42   History: 01/20/12 - Armin
43        akuster@mvista.com
44        ported up to 2.4.16+   
45
46   Version 02/03/25 - Armin
47       converted to ocp format
48       removed commented out or #if 0 code
49       added Gérard Basler's fix to iic_combined_transaction() such that it
50       returns the number of successfully completed transfers .
51*/
52
53
54#include <linux/kernel.h>
55#include <linux/module.h>
56#include <linux/delay.h>
57#include <linux/slab.h>
58#include <linux/init.h>
59#include <linux/errno.h>
60#include <linux/sched.h>
61#include "i2c.h"
62#include "i2c-algo-ibm_ocp.h"
63#include <asm/ocp.h>
64
65
66/* ----- global defines ----------------------------------------------- */
67#define DEB(x) if (i2c_debug>=1) x
68#define DEB2(x) if (i2c_debug>=2) x
69#define DEB3(x) if (i2c_debug>=3) x /* print several statistical values*/
70#define DEBPROTO(x) if (i2c_debug>=9) x;
71        /* debug the protocol by showing transferred bits */
72#define DEF_TIMEOUT 5
73
74
75/* ----- global variables --------------------------------------------- */
76
77
78/* module parameters:
79 */
80static int i2c_debug=0;
81
82/* --- setting states on the bus with the right timing: --------------- */
83
84#define iic_outb(adap, reg, val) adap->setiic(adap->data, (int) &(reg), val)
85#define iic_inb(adap, reg) adap->getiic(adap->data, (int) &(reg))
86
87#define IICO_I2C_SDAHIGH        0x0780
88#define IICO_I2C_SDALOW         0x0781
89#define IICO_I2C_SCLHIGH        0x0782
90#define IICO_I2C_SCLLOW         0x0783
91#define IICO_I2C_LINEREAD       0x0784
92
93#define IIC_SINGLE_XFER         0
94#define IIC_COMBINED_XFER       1
95
96#define IIC_ERR_LOST_ARB        -2
97#define IIC_ERR_INCOMPLETE_XFR  -3
98#define IIC_ERR_NACK            -1
99
100/* --- other auxiliary functions -------------------------------------- */
101
102
103//
104// Description: Puts this process to sleep for a period equal to timeout
105//
106static inline void iic_sleep(unsigned long timeout)
107{
108        schedule_timeout( timeout * HZ);
109}
110
111
112//
113// Description: This performs the IBM PPC 405 IIC initialization sequence
114// as described in the PPC405GP data book.
115//
116static int iic_init (struct i2c_algo_iic_data *adap)
117{
118        struct iic_regs *iic;   
119        struct iic_ibm *adap_priv_data = adap->data;
120        unsigned short  retval;
121        iic = (struct iic_regs *) adap_priv_data->iic_base;
122
123        /* Clear master low master address */
124        iic_outb(adap,iic->lmadr, 0);
125
126        /* Clear high master address */
127        iic_outb(adap,iic->hmadr, 0);
128
129        /* Clear low slave address */
130        iic_outb(adap,iic->lsadr, 0);
131
132        /* Clear high slave address */
133        iic_outb(adap,iic->hsadr, 0);
134
135        /* Clear status */
136        iic_outb(adap,iic->sts, 0x0a);
137
138        /* Clear extended status */
139        iic_outb(adap,iic->extsts, 0x8f);
140
141        /* Set clock division */
142        iic_outb(adap,iic->clkdiv, 0x04);
143
144        retval = iic_inb(adap, iic->clkdiv);
145        DEB(printk("iic_init: CLKDIV register = %x\n", retval));
146
147        /* Enable interrupts on Requested Master Transfer Complete */
148        iic_outb(adap,iic->intmsk, 0x01);
149
150        /* Clear transfer count */
151        iic_outb(adap,iic->xfrcnt, 0x0);
152
153        /* Clear extended control and status */
154        iic_outb(adap,iic->xtcntlss, 0xf0);
155
156        /* Set mode control (flush master data buf, enable hold SCL, exit */
157        /* unknown state.                                                 */
158        iic_outb(adap,iic->mdcntl, 0x47);
159
160        /* Clear control register */
161        iic_outb(adap,iic->cntl, 0x0);
162
163        DEB2(printk(KERN_DEBUG "iic_init: Initialized IIC on PPC 405\n"));
164        return 0;
165}
166
167
168//
169// Description: After we issue a transaction on the IIC bus, this function
170// is called.  It puts this process to sleep until we get an interrupt from
171// from the controller telling us that the transaction we requested in complete.
172//
173static int wait_for_pin(struct i2c_algo_iic_data *adap, int *status) 
174{
175
176        int timeout = DEF_TIMEOUT;
177        int retval;
178        struct iic_regs *iic;
179        struct iic_ibm *adap_priv_data = adap->data;
180        iic = (struct iic_regs *) adap_priv_data->iic_base;
181
182
183        *status = iic_inb(adap, iic->sts);
184#ifndef STUB_I2C
185
186        while (timeout-- && (*status & 0x01)) {
187           adap->waitforpin(adap->data);
188           *status = iic_inb(adap, iic->sts);
189        }
190#endif
191        if (timeout <= 0) {
192           /* Issue stop signal on the bus, and force an interrupt */
193           retval = iic_inb(adap, iic->cntl);
194           iic_outb(adap, iic->cntl, retval | 0x80);
195           /* Clear status register */
196           iic_outb(adap, iic->sts, 0x0a);
197           /* Exit unknown bus state */
198           retval = iic_inb(adap, iic->mdcntl);
199           iic_outb(adap, iic->mdcntl, (retval | 0x02));
200
201           // Check the status of the controller.  Does it still see a
202           // pending transfer, even though we've tried to stop any
203           // ongoing transaction?
204           retval = iic_inb(adap, iic->sts);
205           retval = retval & 0x01;
206           if(retval) {
207              // The iic controller is hosed.  It is not responding to any
208              // of our commands.  We have already tried to force it into
209              // a known state, but it has not worked.  Our only choice now
210              // is a soft reset, which will clear all registers, and force
211              // us to re-initialize the controller.
212              /* Soft reset */
213              iic_outb(adap, iic->xtcntlss, 0x01);
214              udelay(500);
215              iic_init(adap);
216              /* Is the pending transfer bit in the sts reg finally cleared? */
217              retval = iic_inb(adap, iic->sts);
218              retval = retval & 0x01;
219              if(retval) {
220                 printk(KERN_CRIT "The IIC Controller is hosed.  A processor reset is required\n");
221              }
222              // For some reason, even though the interrupt bit in this
223              // register was set during iic_init, it didn't take.  We
224              // need to set it again.  Don't ask me why....this is just what
225              // I saw when testing timeouts.
226              iic_outb(adap, iic->intmsk, 0x01);
227           }
228           return(-1);
229        }
230        else
231           return(0);
232}
233
234
235//------------------------------------
236// Utility functions
237//
238
239
240//
241// Description: Look at the status register to see if there was an error
242// in the requested transaction.  If there is, look at the extended status
243// register and determine the exact cause.
244//
245int analyze_status(struct i2c_algo_iic_data *adap, int *error_code)
246{
247   int ret;
248   struct iic_regs *iic;
249   struct iic_ibm *adap_priv_data = adap->data;
250   iic = (struct iic_regs *) adap_priv_data->iic_base;
251
252       
253   ret = iic_inb(adap, iic->sts);
254   if(ret & 0x04) {
255      // Error occurred
256      ret = iic_inb(adap, iic->extsts);
257      if(ret & 0x04) {
258         // Lost arbitration
259         *error_code =  IIC_ERR_LOST_ARB;
260      }
261      if(ret & 0x02) {
262         // Incomplete transfer
263         *error_code = IIC_ERR_INCOMPLETE_XFR;
264      }
265      if(ret & 0x01) {
266         // Master transfer aborted by a NACK during the transfer of the
267         // address byte
268         *error_code = IIC_ERR_NACK;
269      }
270      return -1;
271   }
272   return 0;
273}
274
275
276//
277// Description: This function is called by the upper layers to do the
278// grunt work for a master send transaction
279//
280static int iic_sendbytes(struct i2c_adapter *i2c_adap,const char *buf,
281                         int count, int xfer_flag)
282{
283        struct iic_regs *iic;
284        struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
285        struct iic_ibm *adap_priv_data = adap->data;
286        int wrcount, status, timeout;
287        int loops, remainder, i, j;
288        int ret, error_code;
289        iic = (struct iic_regs *) adap_priv_data->iic_base;
290
291 
292        if( count == 0 ) return 0;
293        wrcount = 0;
294        loops =  count / 4;
295        remainder = count % 4;
296
297        if((loops > 1) && (remainder == 0)) {
298           for(i=0; i<(loops-1); i++) {
299              //
300              // Write four bytes to master data buffer
301              //
302              for(j=0; j<4; j++) {
303                 iic_outb(adap, iic->mdbuf, 
304                 buf[wrcount++]);
305              }
306              //
307              // Issue command to IICO device to begin transmission
308              //
309              iic_outb(adap, iic->cntl, 0x35);
310              //
311              // Wait for transmission to complete.  When it does,
312              //loop to the top of the for statement and write the
313              // next four bytes.
314              //
315              timeout = wait_for_pin(adap, &status);
316              if(timeout < 0) {
317                 //
318                 // Error handling
319                 //
320                 //printk(KERN_ERR "Error: write timeout\n");
321                 return wrcount;
322              }
323              ret = analyze_status(adap, &error_code);
324              if(ret < 0) {
325                 if(error_code == IIC_ERR_INCOMPLETE_XFR) {
326                    // Return the number of bytes transferred
327                    ret = iic_inb(adap, iic->xfrcnt);
328                    ret = ret & 0x07;
329                    return (wrcount-4+ret);
330                 }
331                 else return error_code;
332              }
333           }
334        }
335        else if((loops >= 1) && (remainder > 0)){
336           //printk(KERN_DEBUG "iic_sendbytes: (loops >= 1)\n");
337           for(i=0; i<loops; i++) {
338              //
339              // Write four bytes to master data buffer
340              //
341              for(j=0; j<4; j++) {
342                 iic_outb(adap, iic->mdbuf,
343                 buf[wrcount++]);
344              }
345              //
346              // Issue command to IICO device to begin transmission
347              //
348              iic_outb(adap, iic->cntl, 0x35);
349              //
350              // Wait for transmission to complete.  When it does,
351              //loop to the top of the for statement and write the
352              // next four bytes.
353              //
354              timeout = wait_for_pin(adap, &status);
355              if(timeout < 0) {
356                 //
357                 // Error handling
358                 //
359                 //printk(KERN_ERR "Error: write timeout\n");
360                 return wrcount;
361              }
362              ret = analyze_status(adap, &error_code);
363              if(ret < 0) {
364                 if(error_code == IIC_ERR_INCOMPLETE_XFR) {
365                    // Return the number of bytes transferred
366                    ret = iic_inb(adap, iic->xfrcnt);
367                    ret = ret & 0x07;
368                    return (wrcount-4+ret);
369                 }
370                 else return error_code;
371              }
372           }
373        }
374
375        //printk(KERN_DEBUG "iic_sendbytes: expedite write\n");
376        if(remainder == 0) remainder = 4;
377        // remainder = remainder - 1;
378        //
379        // Write the remaining bytes (less than or equal to 4)
380        //
381        for(i=0; i<remainder; i++) {
382           iic_outb(adap, iic->mdbuf, buf[wrcount++]);
383           //printk(KERN_DEBUG "iic_sendbytes:  data transferred = %x, wrcount = %d\n", buf[wrcount-1], (wrcount-1));
384        }
385        //printk(KERN_DEBUG "iic_sendbytes: Issuing write\n");
386
387        if(xfer_flag == IIC_COMBINED_XFER) {
388           iic_outb(adap, iic->cntl, (0x09 | ((remainder-1) << 4)));
389        }
390        else {
391           iic_outb(adap, iic->cntl, (0x01 | ((remainder-1) << 4)));
392        }
393        DEB2(printk(KERN_DEBUG "iic_sendbytes: Waiting for interrupt\n"));
394        timeout = wait_for_pin(adap, &status);
395        if(timeout < 0) {
396           //
397           // Error handling
398           //
399           //printk(KERN_ERR "Error: write timeout\n");
400           return wrcount;
401        }
402        ret = analyze_status(adap, &error_code);
403        if(ret < 0) {
404           if(error_code == IIC_ERR_INCOMPLETE_XFR) {
405              // Return the number of bytes transferred
406              ret = iic_inb(adap, iic->xfrcnt);
407              ret = ret & 0x07;
408              return (wrcount-4+ret);
409           }
410           else return error_code;
411        }
412        DEB2(printk(KERN_DEBUG "iic_sendbytes: Got interrupt\n"));
413        return wrcount;
414}
415
416
417//
418// Description: Called by the upper layers to do the grunt work for
419// a master read transaction.
420//
421static int iic_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count, int xfer_type)
422{
423        struct iic_regs *iic;
424        int rdcount=0, i, status, timeout;
425        struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
426        struct iic_ibm *adap_priv_data = adap->data;
427        int loops, remainder, j;
428        int ret, error_code;
429        iic = (struct iic_regs *) adap_priv_data->iic_base;
430
431        if(count == 0) return 0;
432        loops = count / 4;
433        remainder = count % 4;
434
435        //printk(KERN_DEBUG "iic_readbytes: loops = %d, remainder = %d\n", loops, remainder);
436
437        if((loops > 1) && (remainder == 0)) {
438        //printk(KERN_DEBUG "iic_readbytes: (loops > 1) && (remainder == 0)\n");
439           for(i=0; i<(loops-1); i++) {
440              //
441              // Issue command to begin master read (4 bytes maximum)
442              //
443              //printk(KERN_DEBUG "--->Issued read command\n");
444              iic_outb(adap, iic->cntl, 0x37);
445              //
446              // Wait for transmission to complete.  When it does,
447              // loop to the top of the for statement and write the
448              // next four bytes.
449              //
450              //printk(KERN_DEBUG "--->Waiting for interrupt\n");
451              timeout = wait_for_pin(adap, &status);
452              if(timeout < 0) {
453                 // Error Handler
454                 //printk(KERN_ERR "Error: read timed out\n");
455                 return rdcount;
456              }
457              //printk(KERN_DEBUG "--->Got interrupt\n");
458
459              ret = analyze_status(adap, &error_code);
460              if(ret < 0) {
461                 if(error_code == IIC_ERR_INCOMPLETE_XFR)
462                    return rdcount;
463                 else
464                    return error_code;
465              }
466
467              for(j=0; j<4; j++) {
468                 // Wait for data to shuffle to top of data buffer
469                 // This value needs to optimized.
470                 udelay(1);
471                 buf[rdcount] = iic_inb(adap, iic->mdbuf);
472                 rdcount++;
473                 //printk(KERN_DEBUG "--->Read one byte\n");
474              }
475           }
476        }
477
478        else if((loops >= 1) && (remainder > 0)){
479        //printk(KERN_DEBUG "iic_readbytes: (loops >=1) && (remainder > 0)\n");
480           for(i=0; i<loops; i++) {
481              //
482              // Issue command to begin master read (4 bytes maximum)
483              //
484              //printk(KERN_DEBUG "--->Issued read command\n");
485              iic_outb(adap, iic->cntl, 0x37);
486              //
487              // Wait for transmission to complete.  When it does,
488              // loop to the top of the for statement and write the
489              // next four bytes.
490              //
491              //printk(KERN_DEBUG "--->Waiting for interrupt\n");
492              timeout = wait_for_pin(adap, &status);
493              if(timeout < 0) {
494                 // Error Handler
495                 //printk(KERN_ERR "Error: read timed out\n");
496                 return rdcount;
497              }
498              //printk(KERN_DEBUG "--->Got interrupt\n");
499
500              ret = analyze_status(adap, &error_code);
501              if(ret < 0) {
502                 if(error_code == IIC_ERR_INCOMPLETE_XFR)
503                    return rdcount;
504                 else
505                    return error_code;
506              }
507
508              for(j=0; j<4; j++) {
509                 // Wait for data to shuffle to top of data buffer
510                 // This value needs to optimized.
511                 udelay(1);
512                 buf[rdcount] = iic_inb(adap, iic->mdbuf);
513                 rdcount++;
514                 //printk(KERN_DEBUG "--->Read one byte\n");
515              }
516           }
517        }
518
519        //printk(KERN_DEBUG "iic_readbytes: expedite read\n");
520        if(remainder == 0) remainder = 4;
521        DEB2(printk(KERN_DEBUG "iic_readbytes: writing %x to IICO_CNTL\n", (0x03 | ((remainder-1) << 4))));
522
523        if(xfer_type == IIC_COMBINED_XFER) {
524           iic_outb(adap, iic->cntl, (0x0b | ((remainder-1) << 4)));
525        }
526        else {
527           iic_outb(adap, iic->cntl, (0x03 | ((remainder-1) << 4)));
528        }
529        DEB2(printk(KERN_DEBUG "iic_readbytes: Wait for pin\n"));
530        timeout = wait_for_pin(adap, &status);
531        DEB2(printk(KERN_DEBUG "iic_readbytes: Got the interrupt\n"));
532        if(timeout < 0) {
533           // Error Handler
534           //printk(KERN_ERR "Error: read timed out\n");
535           return rdcount;
536        }
537
538        ret = analyze_status(adap, &error_code);
539        if(ret < 0) {
540           if(error_code == IIC_ERR_INCOMPLETE_XFR)
541              return rdcount;
542           else
543              return error_code;
544        }
545
546        //printk(KERN_DEBUG "iic_readbyte: Begin reading data buffer\n");
547        for(i=0; i<remainder; i++) {
548           buf[rdcount] = iic_inb(adap, iic->mdbuf);
549           // printk(KERN_DEBUG "iic_readbytes:  Character read = %x\n", buf[rdcount]);
550           rdcount++;
551        }
552
553        return rdcount;
554}
555
556
557//
558// Description:  This function implements combined transactions.  Combined
559// transactions consist of combinations of reading and writing blocks of data.
560// Each transfer (i.e. a read or a write) is separated by a repeated start
561// condition.
562//
563static int iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) 
564{
565   int i;
566   struct i2c_msg *pmsg;
567   int ret;
568
569   DEB2(printk(KERN_DEBUG "Beginning combined transaction\n"));
570        for(i=0; i < num; i++) {
571                pmsg = &msgs[i];
572                if(pmsg->flags & I2C_M_RD) {
573
574                        // Last read or write segment needs to be terminated with a stop
575                        if(i < num-1) {
576                                DEB2(printk(KERN_DEBUG "This one is a read\n"));
577                        }
578                        else {
579                                DEB2(printk(KERN_DEBUG "Doing the last read\n"));
580                        }
581                        ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, (i < num-1) ? IIC_COMBINED_XFER : IIC_SINGLE_XFER);
582
583                        if (ret != pmsg->len) {
584                                DEB2(printk("i2c-algo-ppc405.o: fail: "
585                                                        "only read %d bytes.\n",ret));
586                                return i;
587                        }
588                        else {
589                                DEB2(printk("i2c-algo-ppc405.o: read %d bytes.\n",ret));
590                        }
591                }
592                else if(!(pmsg->flags & I2C_M_RD)) {
593
594                        // Last read or write segment needs to be terminated with a stop
595                        if(i < num-1) {
596                                DEB2(printk(KERN_DEBUG "This one is a write\n"));
597                        }
598                        else {
599                                DEB2(printk(KERN_DEBUG "Doing the last write\n"));
600                        }
601                        ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, (i < num-1) ? IIC_COMBINED_XFER : IIC_SINGLE_XFER);
602
603                        if (ret != pmsg->len) {
604                                DEB2(printk("i2c-algo-ppc405.o: fail: "
605                                                        "only wrote %d bytes.\n",ret));
606                                return i;
607                        }
608                        else {
609                                DEB2(printk("i2c-algo-ppc405.o: wrote %d bytes.\n",ret));
610                        }
611                }
612        }
613 
614        return num;
615}
616
617
618//
619// Description: Whenever we initiate a transaction, the first byte clocked
620// onto the bus after the start condition is the address (7 bit) of the
621// device we want to talk to.  This function manipulates the address specified
622// so that it makes sense to the hardware when written to the IIC peripheral.
623//
624// Note: 10 bit addresses are not supported in this driver, although they are
625// supported by the hardware.  This functionality needs to be implemented.
626//
627static inline int iic_doAddress(struct i2c_algo_iic_data *adap,
628                                struct i2c_msg *msg, int retries) 
629{
630        struct iic_regs *iic;
631        unsigned short flags = msg->flags;
632        unsigned char addr;
633        struct iic_ibm *adap_priv_data = adap->data;
634        iic = (struct iic_regs *) adap_priv_data->iic_base;
635
636//
637// The following segment for 10 bit addresses needs to be ported
638//
639/* Ten bit addresses not supported right now
640        if ( (flags & I2C_M_TEN)  ) {
641                // a ten bit address
642                addr = 0xf0 | (( msg->addr >> 7) & 0x03);
643                DEB2(printk(KERN_DEBUG "addr0: %d\n",addr));
644                // try extended address code...
645                ret = try_address(adap, addr, retries);
646                if (ret!=1) {
647                        printk(KERN_ERR "iic_doAddress: died at extended address code.\n");
648                        return -EREMOTEIO;
649                }
650                // the remaining 8 bit address
651                iic_outb(adap,msg->addr & 0x7f);
652                // Status check comes here
653                if (ret != 1) {
654                        printk(KERN_ERR "iic_doAddress: died at 2nd address code.\n");
655                        return -EREMOTEIO;
656                }
657                if ( flags & I2C_M_RD ) {
658                        i2c_repstart(adap);
659                        // okay, now switch into reading mode
660                        addr |= 0x01;
661                        ret = try_address(adap, addr, retries);
662                        if (ret!=1) {
663                                printk(KERN_ERR "iic_doAddress: died at extended address code.\n");
664                                return -EREMOTEIO;
665                        }
666                }
667        } else ----------> // normal 7 bit address
668
669Ten bit addresses not supported yet */
670
671        addr = ( msg->addr << 1 );
672        if (flags & I2C_M_RD )
673                addr |= 1;
674        if (flags & I2C_M_REV_DIR_ADDR )
675                addr ^= 1;
676        //
677        // Write to the low slave address
678        //
679        iic_outb(adap, iic->lmadr, addr);
680        //
681        // Write zero to the high slave register since we are
682        // only using 7 bit addresses
683        //
684        iic_outb(adap, iic->hmadr, 0);
685
686        return 0;
687}
688
689
690//
691// Description: Prepares the controller for a transaction (clearing status
692// registers, data buffers, etc), and then calls either iic_readbytes or
693// iic_sendbytes to do the actual transaction.
694//
695static int iic_xfer(struct i2c_adapter *i2c_adap,
696                    struct i2c_msg msgs[], 
697                    int num)
698{
699        struct iic_regs *iic;
700        struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
701        struct iic_ibm *adap_priv_data = adap->data;
702        struct i2c_msg *pmsg;
703        int i = 0;
704        int ret;
705        iic = (struct iic_regs *) adap_priv_data->iic_base;
706
707        pmsg = &msgs[i];
708
709        //
710        // Clear status register
711        //
712        DEB2(printk(KERN_DEBUG "iic_xfer: iic_xfer: Clearing status register\n"));
713        iic_outb(adap, iic->sts, 0x0a);
714
715        //
716        // Wait for any pending transfers to complete
717        //
718        DEB2(printk(KERN_DEBUG "iic_xfer: Waiting for any pending transfers to complete\n"));
719        while((ret = iic_inb(adap, iic->sts)) == 0x01) {
720                ;
721        }
722
723        //
724        // Flush master data buf
725        //
726        DEB2(printk(KERN_DEBUG "iic_xfer: Clearing master data buffer\n"));             
727        ret = iic_inb(adap, iic->mdcntl);
728        iic_outb(adap, iic->mdcntl, ret | 0x40);
729
730        //
731        // Load slave address
732        //
733        DEB2(printk(KERN_DEBUG "iic_xfer: Loading slave address\n"));
734        ret = iic_doAddress(adap, pmsg, i2c_adap->retries);
735
736        //
737        // Check to see if the bus is busy
738        //
739        ret = iic_inb(adap, iic->extsts);
740        // Mask off the irrelevent bits
741        ret = ret & 0x70;
742        // When the bus is free, the BCS bits in the EXTSTS register are 0b100
743        if(ret != 0x40) return IIC_ERR_LOST_ARB;
744
745        //
746        // Combined transaction (read and write)
747        //
748        if(num > 1) {
749           DEB2(printk(KERN_DEBUG "iic_xfer: Call combined transaction\n"));
750           ret = iic_combined_transaction(i2c_adap, msgs, num);
751        }
752        //
753        // Read only
754        //
755        else if((num == 1) && (pmsg->flags & I2C_M_RD)) {
756           //
757           // Tell device to begin reading data from the  master data
758           //
759           DEB2(printk(KERN_DEBUG "iic_xfer: Call adapter's read\n"));
760           ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
761        } 
762        //
763        // Write only
764        //
765        else if((num == 1 ) && (!(pmsg->flags & I2C_M_RD))) {
766           //
767           // Write data to master data buffers and tell our device
768           // to begin transmitting
769           //
770           DEB2(printk(KERN_DEBUG "iic_xfer: Call adapter's write\n"));
771           ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
772        }       
773
774        return ret;   
775}
776
777
778//
779// Description: Implements device specific ioctls.  Higher level ioctls can
780// be found in i2c-core.c and are typical of any i2c controller (specifying
781// slave address, timeouts, etc).  These ioctls take advantage of any hardware
782// features built into the controller for which this algorithm-adapter set
783// was written.  These ioctls allow you to take control of the data and clock
784// lines on the IBM PPC 405 IIC controller and set the either high or low,
785// similar to a GPIO pin.
786//
787static int algo_control(struct i2c_adapter *adapter, 
788        unsigned int cmd, unsigned long arg)
789{
790        struct iic_regs *iic;
791        struct i2c_algo_iic_data *adap = adapter->algo_data;
792        struct iic_ibm *adap_priv_data = adap->data;
793        int ret=0;
794        int lines;
795        iic = (struct iic_regs *) adap_priv_data->iic_base;
796
797        lines = iic_inb(adap, iic->directcntl);
798
799        if (cmd == IICO_I2C_SDAHIGH) {
800              lines = lines & 0x01;
801              if( lines ) lines = 0x04;
802              else lines = 0;
803              iic_outb(adap, iic->directcntl,(0x08|lines));
804        }
805        else if (cmd == IICO_I2C_SDALOW) {
806              lines = lines & 0x01;
807              if( lines ) lines = 0x04;
808              else lines = 0;
809              iic_outb(adap, iic->directcntl,(0x00|lines));
810        }
811        else if (cmd == IICO_I2C_SCLHIGH) {
812              lines = lines & 0x02;
813              if( lines ) lines = 0x08;
814              else lines = 0;
815              iic_outb(adap, iic->directcntl,(0x04|lines));
816        }
817        else if (cmd == IICO_I2C_SCLLOW) {
818              lines = lines & 0x02;
819              if( lines ) lines = 0x08;
820              else lines = 0;
821              iic_outb(adap, iic->directcntl,(0x00|lines));
822        }
823        else if (cmd == IICO_I2C_LINEREAD) {
824              ret = lines;
825        }
826        return ret;
827}
828
829
830static u32 iic_func(struct i2c_adapter *adap)
831{
832        return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 
833               I2C_FUNC_PROTOCOL_MANGLING; 
834}
835
836
837/* -----exported algorithm data: -------------------------------------  */
838
839static struct i2c_algorithm iic_algo = {
840        .owner          = THIS_MODULE,
841        .name           = "IBM on-chip IIC algorithm",
842        .id             = I2C_ALGO_OCP,
843        .master_xfer    = iic_xfer,
844        .algo_control   = algo_control,
845        .functionality  = iic_func,
846};
847
848/*
849 * registering functions to load algorithms at runtime
850 */
851
852
853//
854// Description: Register bus structure
855//
856int i2c_ocp_add_bus(struct i2c_adapter *adap)
857{
858        struct i2c_algo_iic_data *iic_adap = adap->algo_data;
859
860        DEB2(printk(KERN_DEBUG "i2c-algo-iic.o: hw routines for %s registered.\n",
861                    adap->name));
862
863        /* register new adapter to i2c module... */
864
865        adap->id |= iic_algo.id;
866        adap->algo = &iic_algo;
867
868        adap->timeout = 100;    /* default values, should       */
869        adap->retries = 3;              /* be replaced by defines       */
870
871        iic_init(iic_adap);
872        i2c_add_adapter(adap);
873        return 0;
874}
875
876
877//
878// Done
879//
880int i2c_ocp_del_bus(struct i2c_adapter *adap)
881{
882        return i2c_del_adapter(adap);
883}
884
885
886EXPORT_SYMBOL(i2c_ocp_add_bus);
887EXPORT_SYMBOL(i2c_ocp_del_bus);
888
889//
890// The MODULE_* macros resolve to nothing if MODULES is not defined
891// when this file is compiled.
892//
893MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
894MODULE_DESCRIPTION("PPC 405 iic algorithm");
895MODULE_LICENSE("GPL");
896
897MODULE_PARM(i2c_debug,"i");
898
899MODULE_PARM_DESC(i2c_debug,
900        "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");
901
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