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fscscy

Revision 3007, 12.7 KB (checked in by khali, 7 years ago)
Backport the cleanups and corrections Rudolf Marek and I did when porting the chips documentation to Linux 2.6.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`

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1	Kernel driver `fscscy.o'
2	======================
3
4	Status: Beta
5	Tested with motherboard D1230
6	Should also work with D1204, D1306 and D1307
7
8	Think twice before you're using the write mode of some
9	variables, especially the watchdog (Not my comment, but it makes
10	good sense to observe :-)
11
12
13	Supported chips:
14	* Fujitsu Siemens Scylla chip
15	Prefix: 'fscscy'
16	Addresses scanned: I2C 0x73
17
18	Author: Martin Knoblauch <mkn@teraport.de>
19
20	Acknowledgement:
21	This code has been greatly inspired by Hermann Jung <hej@odn.de>
22	and his work on the Poseidon driver (fscpos)
23
24
25	Module Parameters
26	-----------------
27
28	* force: short array (min = 1, max = 48)
29	List of adapter,address pairs to boldly assume to be present
30	* ignore: short array (min = 1, max = 48)
31	List of adapter,address pairs not to scan
32	* ignore_range: short array (min = 1, max = 48)
33	List of adapter,start-addr,end-addr triples not to scan
34	* probe: short array (min = 1, max = 48)
35	List of adapter,address pairs to scan additionally
36	* probe_range: short array (min = 1, max = 48)
37	List of adapter,start-addr,end-addr triples to scan additionally
38
39
40	Description
41	-----------
42
43	This driver implements support for the Fujitsu Siemens Scylla chip.
44	The code is based on the "fscpos" driver for the FSC Poseidon chip.
45	In fact, it seems the Scylla is a superset of the "Poseidon", "Poseidon II"
46	and "Hydra" chips.
47
48	The register readings/setting have been deduced from the 'Register Set
49	Specification BMC Poseidon based Systemboard' by Fujitsu Siemens and the
50	"sbbmon.ini" file from the Fujitsu-Siemens ServerView software.
51
52	The scylla chip implements a hardware based system management,
53	e.g. for controlling fan speed and core voltage.
54	There is also a watchdog counter on the chip which can trigger
55	an alarm and even shutdown the system. See above for more details about using
56	the watchdog feature.
57
58	The chip provides four temperature values (cpu0/1, motherboard and auxiliary),
59	three current values (12 volt, 5 volt and battery) and up to
60	six fans (power supply, cpu and auxiliary).
61
62	Temperatures are measured in degrees Celsius. The resolution is 1 degree.
63	In addition to state and actual temperature, the temperature sensors also export
64	a LIMIT temperature for each sensor. The meaning of the information itself is
65	obvious. The rest is guesswork. It likely triggers an alarm/event as soon as it is
66	reached. The authors feeling is that it is even a writeable register. But beeing of
67	the cautios kind he did not implement writing the LIMIT resister. The driver itself
68	keeps track of the minimum and maximum temperatures since module load. The more often
69	the module is accessed, the more meaningful these values are.
70
71	Fan rotation speeds are reported in RPM (rotations per minute).
72	The value can be divided by a programmable divider (1, 2, 4 or 8) which
73	is stored on the chip.
74
75	Voltage sensors (also known as IN sensors) report their values in volts.
76
77	All values are reported as final values from the driver.
78	There is no need for further calculations.
79
80
81	Using The Watchdog
82	------------------
83
84	This part was mostly contributed by A'rpi <arpi@thot.banki.hu>. Thanks!
85	I (Jean Delvare) edited the text for greater clarity, mainly to integrate
86	the e-mail exchange I and A'rpi had as a sequel of the original report.
87	Here it goes.
88
89	I've spent few hours experiencing with the watchdog feature of the Fujitsu
90	Siemens server board (don't ask the model name, what I know is that it uses
91	Serverworks CSB5 chipset) using lm_sensors' fscscy driver.
92
93	OK, so there is /proc/sys/dev/sensors/fscscy-i2c-0-73/wdog, containing 3
94	8-bit values for the 3 watchdog registers.
95
96	The first one is the time counter, it counts backwards. It's in 2 seconds
97	base, so writting 30 there means 60 seconds delay. It seems the whole range
98	(0 to 255) is supported, so up to 510 seconds (8.5 minutes). Writting 0 means
99	immediate hardware reset. The value you can read back is the same as you wrote
100	there, not the current value of the counter (as I expected).
101
102	The second number is supposed to be a state register. It doesn't matter what
103	value I put there. It's always 0. Even if I write a non-zero value there, i got
104	0 back. Maybe it's non-zero at the moment of reset :)
105
106	The third is the control register, with 5th (value 16), 6th (value 32) and 8th
107	(value 128) bits used only. If I write 16 or 144 (128+16), it means system
108	reset when the counter reaches 0. If I add 32 (for a value of 48 or 176), no
109	reset will occur.
110
111	So, the world's simplest watchdog using this mainboard:
112
113	while true ; do
114	echo 30 0 16 > /proc/sys/dev/sensors/fscscy-i2c-0-73/wdog
115	sleep 10
116	done
117
118	It does hardware reset after 1 minute, if this script is killed or system
119	hang-up occurs. Adjust the 30 and 10 values according to you needs, but
120	remember you must sleep less than the reset countdown time (here, 30*2-10
121	gives us a 50 seconds margin, which is more than enough).
122
123	Also note that BIOS has a strange setting, named 'OS Boot Retry Count', set
124	to 0 by default, it changes watchdog behaviour to power off instead of reset.
125	(0=poweroff 1..7=reset). It took me a while to find this. This behavior is
126	probably related to the "Reset Limit" parameter defined by the ACPI
127	specification (3.3.24 System Reset (Type 23)). It sets how many unintentional
128	resets can be performed in a row before giving up (and shut down).
129
130	Please add the above to the documentation (doc/chips/fscscy), so i can save
131	a few hours of resetting for other people :)
132
133
134	Chip Features
135	-------------
136
137	Chip `fscscy'
138	LABEL LABEL CLASS COMPUTE CLASS ACCESS MAGNITUDE
139	rev NONE NONE R 0
140	event NONE NONE R 0
141	control NONE NONE RW 0
142	volt12 NONE NONE R 2
143	volt5 NONE NONE R 2
144	voltbatt NONE NONE R 2
145	temp1 NONE NONE R 0
146	temp2 NONE NONE R 0
147	temp3 NONE NONE R 0
148	temp4 NONE NONE R 0
149	temp1_state temp1 temp1 RW 0
150	temp2_state temp2 temp2 RW 0
151	temp3_state temp3 temp3 RW 0
152	temp4_state temp4 temp4 RW 0
153	temp1_lim temp1 temp1 R* 0
154	temp2_lim temp2 temp2 R* 0
155	temp3_lim temp3 temp3 R* 0
156	temp4_lim temp4 temp4 R* 0
157	temp1_min temp1 temp1 R 0
158	temp2_min temp2 temp2 R 0
159	temp3_min temp3 temp3 R 0
160	temp4_min temp4 temp4 R 0
161	temp1_max temp1 temp1 R 0
162	temp2_max temp2 temp2 R 0
163	temp3_max temp3 temp3 R 0
164	temp4_max temp4 temp4 R 0
165	fan1 NONE NONE R 0
166	fan2 NONE NONE R 0
167	fan3 NONE NONE R 0
168	fan4 NONE NONE R 0
169	fan5 NONE NONE R 0
170	fan6 NONE NONE R 0
171	fan1_min fan1 fan1 RW 0
172	fan2_min fan2 fan2 RW 0
173	fan3_min fan3 fan3 RW 0
174	fan4_min fan4 fan4 RW 0
175	fan5_min fan5 fan5 RW 0
176	fan6_min fan6 fan6 RW 0
177	fan1_state fan1 fan1 RW 0
178	fan2_state fan2 fan2 RW 0
179	fan3_state fan3 fan3 RW 0
180	fan4_state fan4 fan4 RW 0
181	fan5_state fan5 fan5 RW 0
182	fan6_state fan6 fan6 RW 0
183	fan1_ripple fan1 fan1 RW 0
184	fan2_ripple fan2 fan2 RW 0
185	fan3_ripple fan3 fan3 RW 0
186	fan4_ripple fan4 fan4 RW 0
187	fan5_ripple fan5 fan5 RW 0
188	fan6_ripple fan6 fan6 RW 0
189	wdog_preset NONE NONE RW 0
190	wdog_state wdog_preset wdog_preset RW 0
191	wdog_control wdog_preset wdog_preset RW 0
192
193	R*: Maybe writable, but due to lack of documentation the author did not dare
194	to implement it :-)
195
196
197	LABEL FEATURE SYMBOL SYSCTL FILE:OFFSET
198	rev FSCSCY_SYSCTL_REV rev:1
199	event FSCSCY_SYSCTL_EVENT event:1
200	control FSCSCY_SYSCTL_CONTROL control:1
201	volt12 FSCSCY_SYSCTL_VOLTAGE1 volt0:1
202	volt5 FSCSCY_SYSCTL_VOLTAGE2 volt1:1
203	voltbatt FSCSCY_SYSCTL_VOLTAGE3 volt2:1
204	temp1 FSCSCY_SYSCTL_TEMP1 temp0:2
205	temp2 FSCSCY_SYSCTL_TEMP2 temp1:2
206	temp3 FSCSCY_SYSCTL_TEMP3 temp2:2
207	temp4 FSCSCY_SYSCTL_TEMP4 temp3:2
208	temp1_state FSCSCY_SYSCTL_TEMP1_STATE temp0:1
209	temp2_state FSCSCY_SYSCTL_TEMP2_STATE temp1:1
210	temp3_state FSCSCY_SYSCTL_TEMP3_STATE temp2:1
211	temp4_state FSCSCY_SYSCTL_TEMP4_STATE temp3:1
212	temp1_lim FSCSCY_SYSCTL_TEMP1_LIM temp0:3
213	temp2_lim FSCSCY_SYSCTL_TEMP2_LIM temp1:3
214	temp3_lim FSCSCY_SYSCTL_TEMP3_LIM temp2:3
215	temp4_lim FSCSCY_SYSCTL_TEMP4_LIM temp3:3
216	temp1_min FSCSCY_SYSCTL_TEMP1_MIN temp0:4
217	temp2_min FSCSCY_SYSCTL_TEMP2_MIN temp1:4
218	temp3_min FSCSCY_SYSCTL_TEMP3_MIN temp2:4
219	temp4_min FSCSCY_SYSCTL_TEMP4_MIN temp3:4
220	temp1_max FSCSCY_SYSCTL_TEMP1_MIN temp0:5
221	temp2_max FSCSCY_SYSCTL_TEMP2_MIN temp1:5
222	temp3_max FSCSCY_SYSCTL_TEMP3_MIN temp2:5
223	temp4_max FSCSCY_SYSCTL_TEMP4_MIN temp3:5
224	fan1 FSCSCY_SYSCTL_FAN1 fan0:4
225	fan2 FSCSCY_SYSCTL_FAN2 fan1:4
226	fan3 FSCSCY_SYSCTL_FAN3 fan2:4
227	fan4 FSCSCY_SYSCTL_FAN4 fan3:4
228	fan5 FSCSCY_SYSCTL_FAN5 fan4:4
229	fan6 FSCSCY_SYSCTL_FAN6 fan5:4
230	fan1_min FSCSCY_SYSCTL_FAN1_MIN fan0:2
231	fan2_min FSCSCY_SYSCTL_FAN2_MIN fan1:2
232	fan3_min FSCSCY_SYSCTL_FAN3_MIN fan2:2
233	fan4_min FSCSCY_SYSCTL_FAN4_MIN fan3:2
234	fan5_min FSCSCY_SYSCTL_FAN5_MIN fan4:2
235	fan6_min FSCSCY_SYSCTL_FAN6_MIN fan5:2
236	fan1_state FSCSCY_SYSCTL_FAN1_STATE fan0:1
237	fan2_state FSCSCY_SYSCTL_FAN2_STATE fan1:1
238	fan3_state FSCSCY_SYSCTL_FAN3_STATE fan2:1
239	fan4_state FSCSCY_SYSCTL_FAN4_STATE fan3:1
240	fan5_state FSCSCY_SYSCTL_FAN5_STATE fan4:1
241	fan6_state FSCSCY_SYSCTL_FAN6_STATE fan5:1
242	fan1_ripple FSCSCY_SYSCTL_FAN1_RIPPLE fan0:3
243	fan2_ripple FSCSCY_SYSCTL_FAN2_RIPPLE fan1:3
244	fan3_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan2:3
245	fan4_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan3:3
246	fan5_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan4:3
247	fan6_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan5:3
248	wdog_preset FSCSCY_SYSCTL_WDOG_PRESET wdog:1
249	wdog_state FSCSCY_SYSCTL_WDOG_STATE wdog:2
250	wdog_control FSCSCY_SYSCTL_WDOG_CONTROL wdog:3
251

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