root/lm-sensors/trunk/doc/busses/i2c-i801

Revision 5231, 3.0 kB (checked in by khali, 2 months ago)

Add Intel ICH10 support.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
Line 
1 Kernel driver `i2c-i801.o'
2
3 Status: Tested and stable.
4         Block reads/writes lightly tested.
5         HW PEC support Beta.
6         I2C Block Read support Beta.
7
8 Supported adapters:
9   * Intel 82801AA and 82801AB (ICH and ICH0 - part of the
10     '810' and '810E' chipsets)
11   * Intel 82801BA (ICH2 - part of the '815E' chipset)
12   * Intel 82801CA/CAM (ICH3)
13   * Intel 82801DB (ICH4)
14   * Intel 82801EB/ER (ICH5)
15   * Intel 6300ESB/ESB2
16   * Intel 82801FB/FR/FW/FRW (ICH6)
17   * Intel ICH7/ICH8/ICH9
18   * Intel Tolapai
19   * Intel ICH10
20     Datasheets: Publicly available at the Intel website
21
22 Authors: Frodo Looijaard <frodol@dds.nl>, Philip Edelbrock
23          <phil@netroedge.com>, and Mark Studebaker <mdsxyz123@yahoo.com>
24
25
26 Module Parameters
27 -----------------
28
29 * force_addr: int
30   Forcibly enable the ICH at the given address. EXTREMELY DANGEROUS!
31
32
33 Description
34 -----------
35
36 The ICH (properly known as the 82801AA), ICH0 (82801AB),
37 ICH2 (82801BA), ICH3 (82801CA/CAM) and later devices
38 are Intel chips that are a part of
39 Intel's '810' chipset for Celeron-based PCs,
40 '810E' chipset for Pentium-based PCs, '815E' chipset, and others.
41
42 The ICH chips contain at least SEVEN separate PCI functions
43 in TWO logical PCI devices.
44 An output of lspci will show something similar to the following:
45
46   00:1e.0 PCI bridge: Intel Corporation: Unknown device 2418 (rev 01)
47   00:1f.0 ISA bridge: Intel Corporation: Unknown device 2410 (rev 01)
48   00:1f.1 IDE interface: Intel Corporation: Unknown device 2411 (rev 01)
49   00:1f.2 USB Controller: Intel Corporation: Unknown device 2412 (rev 01)
50   00:1f.3 Unknown class [0c05]: Intel Corporation: Unknown device 2413 (rev 01)
51
52 The SMBus controller is function 3 in device 1f.
53 Class 0c05 is SMBus Serial Controller.
54
55 If you do NOT see the 24x3 device at function 3, and you can't
56 figure out any way in the BIOS to enable it,
57 (and especially if you have an Asus P4B board),
58 see prog/hotplug/README.p4b.
59
60 The ICH chips are quite similar to Intel's PIIX4 chip,
61 at least in the SMBus controller.
62
63 See the file i2c-piix4 for some additional information.
64
65
66 Process Call Support
67 --------------------
68
69 Not supported.
70
71
72 I2C Block Read Support
73 ----------------------
74
75 The ICH4 supports a special 3-byte address (command code
76 plus 2 more bytes) I2C block read.
77 The driver and the kernel i2c protocol stack do not
78 support this.
79 The ICH5 and higher support a standard 1-byte address (command code)
80 I2C block read. The driver does support this.
81
82
83 SMBus 2.0 Support
84 -----------------
85
86 The 82801DB (ICH4) and later chips support several SMBus 2.0 features.
87 Kernel and driver support are as follows:
88
89 Feature         Kernel          Driver
90 Slave mode      no              no
91 Host notify     no              no
92 Block PEC       yes             yes
93 Hardware PEC    yes             yes
94
95
96 Other ICH4 and later Features
97 -----------------------------
98
99 The following additional features are also _not_ supported:
100
101 32 Byte buffer
102
103
104 **********************
105 The lm_sensors project gratefully acknowledges the support of
106 Texas Instruments in the initial development of this driver.
107
108 The lm_sensors project gratefully acknowledges the support of
109 Intel in the development of SMBus 2.0 / ICH4 features of this driver.
Note: See TracBrowser for help on using the browser.