| 1 | Kernel driver `i2c-i801.o' |
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| 2 | |
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| 3 | Status: Tested and stable. |
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| 4 | Block reads/writes lightly tested. |
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| 5 | HW PEC support Beta. |
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| 6 | I2C Block Read support Beta. |
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| 7 | |
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| 8 | Supported adapters: |
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| 9 | * Intel 82801AA and 82801AB (ICH and ICH0 - part of the |
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| 10 | '810' and '810E' chipsets) |
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| 11 | * Intel 82801BA (ICH2 - part of the '815E' chipset) |
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| 12 | * Intel 82801CA/CAM (ICH3) |
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| 13 | * Intel 82801DB (ICH4) |
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| 14 | * Intel 82801EB/ER (ICH5) |
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| 15 | * Intel 6300ESB/ESB2 |
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| 16 | * Intel 82801FB/FR/FW/FRW (ICH6) |
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| 17 | * Intel ICH7/ICH8/ICH9 |
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| 18 | Datasheets: Publicly available at the Intel website |
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| 19 | |
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| 20 | Authors: Frodo Looijaard <frodol@dds.nl>, Philip Edelbrock |
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| 21 | <phil@netroedge.com>, and Mark Studebaker <mdsxyz123@yahoo.com> |
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| 22 | |
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| 23 | |
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| 24 | Module Parameters |
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| 25 | ----------------- |
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| 26 | |
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| 27 | * force_addr: int |
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| 28 | Forcibly enable the ICH at the given address. EXTREMELY DANGEROUS! |
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| 29 | |
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| 30 | |
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| 31 | Description |
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| 32 | ----------- |
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| 33 | |
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| 34 | The ICH (properly known as the 82801AA), ICH0 (82801AB), |
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| 35 | ICH2 (82801BA), ICH3 (82801CA/CAM) and later devices |
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| 36 | are Intel chips that are a part of |
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| 37 | Intel's '810' chipset for Celeron-based PCs, |
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| 38 | '810E' chipset for Pentium-based PCs, '815E' chipset, and others. |
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| 39 | |
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| 40 | The ICH chips contain at least SEVEN separate PCI functions |
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| 41 | in TWO logical PCI devices. |
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| 42 | An output of lspci will show something similar to the following: |
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| 43 | |
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| 44 | 00:1e.0 PCI bridge: Intel Corporation: Unknown device 2418 (rev 01) |
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| 45 | 00:1f.0 ISA bridge: Intel Corporation: Unknown device 2410 (rev 01) |
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| 46 | 00:1f.1 IDE interface: Intel Corporation: Unknown device 2411 (rev 01) |
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| 47 | 00:1f.2 USB Controller: Intel Corporation: Unknown device 2412 (rev 01) |
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| 48 | 00:1f.3 Unknown class [0c05]: Intel Corporation: Unknown device 2413 (rev 01) |
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| 49 | |
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| 50 | The SMBus controller is function 3 in device 1f. |
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| 51 | Class 0c05 is SMBus Serial Controller. |
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| 52 | |
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| 53 | If you do NOT see the 24x3 device at function 3, and you can't |
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| 54 | figure out any way in the BIOS to enable it, |
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| 55 | (and especially if you have an Asus P4B board), |
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| 56 | see prog/hotplug/README.p4b. |
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| 57 | |
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| 58 | The ICH chips are quite similar to Intel's PIIX4 chip, |
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| 59 | at least in the SMBus controller. |
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| 60 | |
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| 61 | See the file i2c-piix4 for some additional information. |
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| 62 | |
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| 63 | |
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| 64 | Process Call Support |
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| 65 | -------------------- |
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| 66 | |
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| 67 | Not supported. |
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| 68 | |
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| 69 | |
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| 70 | I2C Block Read Support |
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| 71 | ---------------------- |
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| 72 | |
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| 73 | The ICH4 supports a special 3-byte address (command code |
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| 74 | plus 2 more bytes) I2C block read. |
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| 75 | The driver and the kernel i2c protocol stack do not |
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| 76 | support this. |
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| 77 | The ICH5 and higher support a standard 1-byte address (command code) |
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| 78 | I2C block read. The driver does support this. |
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| 79 | |
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| 80 | |
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| 81 | SMBus 2.0 Support |
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| 82 | ----------------- |
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| 83 | |
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| 84 | The 82801DB (ICH4) and later chips support several SMBus 2.0 features. |
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| 85 | Kernel and driver support are as follows: |
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| 86 | |
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| 87 | Feature Kernel Driver |
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| 88 | Slave mode no no |
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| 89 | Host notify no no |
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| 90 | Block PEC yes yes |
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| 91 | Hardware PEC yes yes |
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| 92 | |
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| 93 | |
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| 94 | Other ICH4 and later Features |
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| 95 | ----------------------------- |
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| 96 | |
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| 97 | The following additional features are also _not_ supported: |
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| 98 | |
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| 99 | 32 Byte buffer |
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| 100 | |
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| 101 | |
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| 102 | ********************** |
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| 103 | The lm_sensors project gratefully acknowledges the support of |
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| 104 | Texas Instruments in the initial development of this driver. |
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| 105 | |
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| 106 | The lm_sensors project gratefully acknowledges the support of |
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| 107 | Intel in the development of SMBus 2.0 / ICH4 features of this driver. |
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