Changeset 4356

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Timestamp:
04/01/07 14:29:24 (1 year ago)
Author:
khali
Message:

Discard 3 out-of-date entries.
Case and spacing fixes.

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  • i2c/trunk/TODO

    r4158 r4356  
    1818* Timing considerations in SMBus emulation with i2c-algo-bit (D.E.): 
    1919  (Note that some of these changes are implemented in i2c-algo-biths) 
    20   The Smbus defines a minimum frequency of 10 KHZ for driving the bus, while 
     20  The SMBus defines a minimum frequency of 10 kHz for driving the bus, while 
    2121  the I2C does not define any minimum frequency. 
    2222  furthermore the maximum time a master is allowed to keep the CLK line high 
    …… 
    2626  It's crucial that masters will obey the last timing consideration, since: 
    2727        1. Slaves may otherwise hang the transaction. 
    28         2. Other masters will assume the bus is idle, initiate their own Smbus 
     28        2. Other masters will assume the bus is idle, initiate their own SMBus 
    2929           transaction, which will lead to corruption of data 
    30            carried over the Smbus. 
     30           carried over the SMBus. 
    3131  Note that a correct arbitration procedure can take 
    3232  place only if masters are "synchronized" meaning, they initiate the 
    3333  transaction at the _same_ time. 
    3434 
    35   Now when implementing the Smbus protocol in SW one has to make sure that in 
     35  Now when implementing the SMBus protocol in SW one has to make sure that in 
    3636  the critical sections in which the CLK is held high, SW is not preempted. 
    3737  Or more simply: SW must disable interrupts at this period of time. 
    …… 
    5151  Although the I2C disallows arbitration between masters while one is sending 
    5252  a restart signal & another sending a data signal, this situation is 
    53   theoretically possible on an Smbus. 
     53  theoretically possible on an SMBus. 
    5454  So you would need to check for arbitration when driving the restart signal 
    5555  too. BTW why is the arbitration check code disabled in the i2c_outb? 
    56  
    57 * Dynamic data length read on BlockRead & BlockProcess calls 
    58   in SMBus emulation with i2c-algo-bit (D.E.):  
    59   These 2 Smbus commands digest the read data in-order to decide on the fly 
    60   how many data bytes to read. 
    61   Such a requirement is not described by the I2C protocol and is not 
    62   implemented in the i2c-algo-bit.c. 
    63   Perhaps we could add a flag which will turn on some digesting code in 
    64   "readbytes" routine which will mimic the Smbus behavior. 
    6556 
    6657* Pre-Post routines with i2c-algo-bit (D.E.):  
    …… 
    114105  block size but the code is designed for the 32 byte limit of 
    115106  SMBus. 
    116  
    117 * Enhance mkpatch so it will patch additional drivers such as 
    118   the Power PC modules to 2.4 kernels that support it. Currently 
    119   these drivers are not patched because it would break 2.2 kernels. 
    120107 
    121108* i2c version strings were added to i2c.h but they are used only 
    …… 
    150137        drivers/usb/ov511.c 
    151138 
    152 * Make sure the /proc registration code in i2c-core uses the same debugging 
    153   code and other conventions as the rest of the file. 
    154  
    155139* Make especially i2c-core SMP-safe. This means: locks around all global 
    156140  variable access, especially during (de)registration activity. 
    …… 
    240224 
    241225We don't want to violate that. If udelay == 5,  
    242 (which implies a 100 KHz clock) that should 
     226(which implies a 100 kHz clock) that should 
    243227be the minimum time high _or_ low for the clock. 
    244228So I don't think your third picture below should be implemented. 
    …… 
    261245 
    262246> We don't want to violate that. If udelay == 5, 
    263 > (which implies a 100 KHz clock) that should 
     247> (which implies a 100 kHz clock) that should 
    264248> be the minimum time high _or_ low for the clock. 
    265249 
    …… 
    468452Start", "Low period of SCL" and "SCL clock frequency". 
    469453With 1us resolution best we can do within fast mode specs is 
    470 udelay=2 and get 250kHz. I think stock kernel tree doesn't export 
     454udelay=2 and get 250 kHz. I think stock kernel tree doesn't export 
    471455anything to improve the resolution, so I will settle for udelay. 
    472456 
    …… 
    540524> > Start", "Low period of SCL" and "SCL clock frequency". 
    541525> > With 1us resolution best we can do within fast mode specs is 
    542 > > udelay=2 and get 250kHz. I think stock kernel tree doesn't export 
     526> > udelay=2 and get 250 kHz. I think stock kernel tree doesn't export 
    543527> > anything to improve the resolution, so I will settle for udelay. 
    544528> >